The present invention relates to a method of manufacturing a semiconductor device and to a semiconductor device, and, in particular, to a method of manufacturing a semiconductor device and to a semiconductor device, the semiconductor device having wiring and a via plug containing copper as a component.
For wiring layers of semiconductor devices in recent years, Cu (copper) damascene wirings having high reliability and high performance have been frequently used. Hereinafter, the conventional manufacturing procedure of Cu damascene wiring in semiconductor devices will be described.
Firstly, over a semiconductor substrate in which electronic parts including transistors have been formed, a first interlayer insulating film is formed. Next, in the first interlayer insulating film, grooves for lower layer wiring having a prescribed shape are formed. Next, over the first interlayer insulating film including a bottom face and a side face of the groove for lower layer wiring, a barrier metal film formed by laminating a TaN film and a Ta film is formed. Then, over the barrier metal film, a Cu seed film is formed.
Next, over the Cu seed film, a plated Cu film is formed by a plating method. The surface of the plated Cu film thus formed is formed so as to be higher than the upper surface of the first interlayer insulating film. Next, a heat treatment is performed for the purpose of growing copper grains of the plated Cu film. After that, an excess Cu film is removed by CMP (Chemical Mechanical Polishing) until the seed Cu film and the first interlayer insulating film having been formed in the groove for lower layer wiring are exposed. As a result, lower layer Cu wiring is formed in the groove for the lower layer wiring.
Next, over the first interlayer insulating film in which the lower layer Cu wiring has been formed, a copper diffusion-preventing film for suppressing the diffusion of Cu into the interlayer insulating film is formed. Then, over the copper diffusion-preventing film, a second interlayer insulating film having insulating material is formed. Next, at a prescribed position of the second interlayer insulating film, a contact hole that reaches the lower layer Cu wiring is formed. Further, in the second interlayer insulating film, grooves for upper layer wiring are formed. Here, a part of the bottom face of the groove for the upper layer wiring is connected with the upper face of the contact hole.
Next, in the contact hole and the groove for the upper layer wiring, a barrier metal film including a TaN film and a Ta film is formed. Next, over the barrier metal film, a Cu seed film is formed. Next, over the Cu seed film, a plated Cu film is formed by a plating method. Then, excess portions of the Cu film are removed by CMP. This results in the formation of upper layer Cu wiring in the upper layer wiring groove, and the formation of a contact plug in the contact hole.
Meanwhile, as prior arts for the Cu damascene wiring, for example, there is Non-patent Document 1 (K. Higashi, H. Yamaguchi, S. Omoto, A. Sakata, T. Katata, N. Matsunaga and H. Shibata, “Highly Reliable PVD/ALD/PVD stacked Barrier Metal Structure for 45 nm-Node Copper Dual-Damascene Interconnects”, International Interconnect Technology Conference 2004). Further, there are Patent Documents 1, 2 and 3 below.    Patent Document 1 (Japanese Unexamined Patent Publication No. 2007-59734) discloses following techniques. At first, in the formation of buried Cu wiring, a Cu alloy containing such metal as Al that has a large diffusion coefficient in Cu and a lower formation energy of the oxide than that of copper is formed as the seed layer. Then, after the wiring Cu is buried, a heat treatment is performed to diffuse the contained metal. Thus, the oxide of the contained metal such as aluminum oxide is formed over the surface of the wiring to constitute a barrier film.    Patent Document 2 (Japanese Unexamined Patent Publication No. 2007-180407) discloses following techniques. Firstly, buried Al-containing Cu wiring is formed by the diffusion of Al from an Al-containing Cu seed layer. Then, aluminum oxide formed over the surface thereof remains as it is, it is removed together with a barrier metal when a connecting via with upper layer wiring is formed, and lower layer CuAl wiring is etched to form a barrier metal and via metal.    Patent Document 3 (Japanese Unexamined Patent Publication No. 2007-67107) discloses following techniques. A treatment is performed in an oxidative atmosphere so as to diffuse contained metals from a seed layer containing other metals (such as Mn and Al) than Cu into copper being wiring metal. This results in the formation of an oxide film of the diffused metal over the surface of the copper wiring metal to form a covering layer.